NDLI: Design And Synthesis Of Clockless Pipelines Based On Self-resetting Stage Logic

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Design And Synthesis Of Clockless Pipelines Based On Self-resetting Stage Logic

Content Provider	Semantic Scholar
Author	Alsharqawi, Abdelhalim
Copyright Year	2005
Abstract	For decades, digital design has been primarily dominated by clocked circuits. With larger scales of integration made possible by improved semiconductor manufacturing techniques, relying on a clock signal to orchestrate logic operations across an entire chip became increasingly difficult. Motivated by this problem, designers are currently considering circuits which can operate without a clock. However, the wide acceptance of these circuits by the digital design community requires two ingredients: (i) a unified design methodology supported by widely available CAD tools, and (ii) a granularity of design techniques suitable for synthesizing large designs. Currently, there is no unified established design methodology to support the design and verification of these circuits. Moreover, the majority of clockless design techniques is conceived at circuit level, and is subsequently so fine-grain, that their application to large designs can have unacceptable area costs. Given these considerations, this dissertation presents a new clockless technique, called self-resetting stage logic (SRSL), in which the computation of a block is reset periodically from within the block itself. SRSL is used as a building block for three coarse-grain pipelining techniques: (i) Stage-controlled self-resetting stage logic (S-SRSL) Pipelines: In these pipelines, the control of the communication between stages is performed locally between each pair of stages. This communication is performed in a uni-directional manner in order to simplify its implementation.
File Format	PDF HTM / HTML
Alternate Webpage(s)	http://stars.library.ucf.edu/cgi/viewcontent.cgi?article=1523&context=etd
Language	English
Access Restriction	Open
Content Type	Text
Resource Type	Article

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