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FPGA Implementation of Efficient Carry-Select Adder Using Verilog HDL
| Content Provider | Semantic Scholar |
|---|---|
| Author | Raju, Lingappagari Kumar, Anil |
| Copyright Year | 2015 |
| Abstract | Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses the logic operations involved in conventional carry select adder (CSLA) and Dual RCA’s based CSLA, binary to excess converter(BEC)-based CSLA ,CLB based CSLA are analyzed to study the data dependence and to identify redundant logic operations. We have eliminated all the redundant logic operations present in the conventional CSLA and proposed a new logic formulation for CSLA. In the proposed scheme, the carry select (CS) operation is scheduled before the calculation offinal-sum, which is different from the conventional approach. Bit patterns of two anticipating carry words (corresponding to Cin= 0 and 1) and fixed Cin bits are used for logic optimization of CS and generation units. An efficient CSLA design is obtained using optimized logic unit. Based on this modification 8-, 16-, 32-, and 64-bit square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ijmetmr.com/oljune2015/LingappagariRaju-DrTippartiAnilKumar-23.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
