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Si nanowire heterostructures as high-performance field-effect transistors
| Content Provider | Semantic Scholar |
|---|---|
| Author | Xiang, Jie Lu, Wenjing Hu, Yongjie Lieber, Charles M. |
| Copyright Year | 2006 |
| Abstract | Semiconducting carbon nanotubes and nanowires are potential alternatives to planar metal-oxide-semiconductor field-effect transistors (MOSFETs) owing, for example, to their unique electronic structure and reduced carrier scattering caused by one-dimensional quantum confinement effects. Studies have demonstrated long carrier mean free paths at room temperature in both carbon nanotubes and Ge/Si core/shell nanowires. In the case of carbon nanotube FETs, devices have been fabricated that work close to the ballistic limit. Applications of highperformance carbon nanotube FETs have been hindered, however, by difficulties in producing uniform semiconducting nanotubes, a factor not limiting nanowires, which have been prepared with reproducible electronic properties in high yield as required for large-scale integrated systems. Yet whether nanowire fieldeffect transistors (NWFETs) can indeed outperform their planar counterparts is still unclear. Here we report studies onGe/Si core/ shell nanowire heterostructures configured as FETs using high-k dielectrics in a top-gate geometry. The clean one-dimensional hole-gas in the Ge/Si nanowire heterostructures and enhanced gate coupling with high-k dielectrics give high-performance FETs values of the scaled transconductance (3.3mS mm) and oncurrent (2.1mA mm) that are three to four times greater than state-of-the-art MOSFETs and are the highest obtained on NWFETs. Furthermore, comparison of the intrinsic switching delay, t 5 CV/I, which represents a key metric for device applications, shows that the performance of Ge/Si NWFETs is comparable to similar length carbon nanotube FETs and substantially exceeds the length-dependent scaling of planar silicon MOSFETs. Silicon and germanium nanowires have been the focus of recent studies of one-dimensional (1D) FETs. However, metal contacts to single-component nanowires generally produce Schottky barriers that limit device performance, and moreover, scattering from charged dopants can also reduce the intrinsic mobility of these nanowire devices. In contrast, we have recently demonstrated transparent contacts and low-bias ballistic transport in undoped Ge/ Si core/shell nanowire heterostructures (Fig. 1a, b), with an estimated scatteringmean free path of,500 nm. The 1D sub-band spacing in the typical 15-nm core Ge/Si nanowires determined through both experimental measurements and theoretical calculations is ,25meV, and thus at room temperature several sub-bands may participate in NWFET transport. While the Ge/Si nanowire devices will not be strictly 1D, the limited number of conduction channels and clean material structure can benefit performance through, for example, a reduction in scattering. To explore the potential of Ge/Si nanowire heterostructures as high-performance FETs we have fabricated (see Methods) devices using thinHfO2 or ZrO2 high-k gate dielectrics and metal top gate electrodes (Fig. 1c, d). Cross-sectional transmission electron microscopy (TEM) images (Fig. 1e) show that both the high-k and metal top gate conform to the approximately circular cross-section of the nanowire, and also verify the Ge/Si core/shell structure. The conformal top gate structure approaches an ideal cylindrical gate geometry, and together with the high-k dielectrics produces a much more efficient gate response than previous studies using lower-k SiO2 dielectric and planar back gates . Typical output and transfer characteristics recorded from a Ge/Si device fabricated in this way with a channel length, L 1⁄4 1 mm and a total diameter of 18 nm (device A) are shown in Fig. 2a, b. The family of Id–Vds curves (Fig. 2a) show that the drain current Id first increases then saturates with increasingly negative drain voltage, similar to a conventional long channel MOSFET. These data also show that Id increases as the gate voltageVg decreases from 1 to22V, and thus that the device is a p-type depletion-mode FET. This p-type FET behaviour is expected from the band diagram in Fig. 1b, where the Fermi level lies below the Ge valence band edge in the absence of a gate. The Id–Vg transfer curve recorded for the drain bias voltage LETTERS |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.hu.seas.ucla.edu/docs/Nature_2006.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
