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High performance horizontal gate-all-around silicon nanowire field-effect transistors.
| Content Provider | Semantic Scholar |
|---|---|
| Author | Shirak, O. Shtempluck, Oleg Kotchtakov, V. Bahir, Gad Yaish, Yuval E. |
| Copyright Year | 2012 |
| Abstract | Semiconducting nanowires have been pointed out as one of the most promising building blocks for submicron electrical applications. These nanometer materials open new opportunities in the area of post-planar traditional metal-oxide-semiconductor devices. Herein, we demonstrate a new technique to fabricate horizontally suspended silicon nanowires with gate-all-around field-effect transistors. We present the design, fabrication and electrical measurements of a high performance transistor with high on current density (~150 μA μm(-1)), high on/off current ratio (10(6)), low threshold voltage (~ - 0.4 V), low subthreshold slope (~100 mV /dec) and high transconductance (g(m) ~ 9.5 μS). These high performance characteristics were possible due to the tight electrostatic coupling of the surrounding gate, which significantly reduced the Schottky-barrier effective height, as was confirmed experimentally in this study. |
| Starting Page | 395202 |
| Ending Page | 395202 |
| Page Count | 1 |
| File Format | PDF HTM / HTML |
| DOI | 10.1088/0957-4484/23/39/395202 |
| Alternate Webpage(s) | http://carbonlab.net.technion.ac.il/files/2013/10/Shirak2012.pdf |
| PubMed reference number | 22971804 |
| Alternate Webpage(s) | https://doi.org/10.1088/0957-4484%2F23%2F39%2F395202 |
| Journal | Medline |
| Volume Number | 23 |
| Issue Number | 39 |
| Journal | Nanotechnology |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
