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DesignCon 2017 Characterization of DDR 4 Receiver Sensitivity Impact on Post-equalization Eye
| Content Provider | Semantic Scholar |
|---|---|
| Author | Wang, Yong Niu, Penglin Rao, Fangyi Wang, Juan |
| Copyright Year | 2016 |
| Abstract | The current DDR4 specification for the receiver (Rx) sensitivity defined at the Rx input does not account for equalization functionalities implemented in advanced Rx designs and may lead to over-design. In this paper we present a novel approach to characterize the Rx sensitivity impact on Rx post-equalization signal. We demonstrate that at the Rx output timing impairment is induced by common mode variation. The resulting jitter can be represented by a deterministic jitter model and incorporated in the statistical eye calculation. Timing margin and jitter in the post-equalization eye is measured at Vref to eliminate over-design. Author(s) Biography Yong Wang is currently a Sr. Director of Engineering at Xilinx leading Device Power and Signal Integrity Group since 2011. His team owns Xilinx product families' SI/PI methodology development, noise/timing/jitter analysis, interface timing such as DDR4/3, and corresponding verification/characterization. Prior to joining Xilinx, Mr. Yong Wang has been system design lead and SI/PI lead of several companies such as NVIDIA, MetaRAM, HP/Intel. He led the world first 16GB and 32GB R-DIMM design, validation and production with patented memory buffer ASIC design when he was system lead with MetaRAM. In NVIDIA/HP/Intel, he provided technical leadership in the areas such as but not limited to, IA-64 system front-side parallel bus channel timing, serial link channel analysis, system level power modeling, on-die power grid noise/timing analysis and timing/noise validation in the lab. Mr. Yong Wang received his M.S. degree in Electrical Engineering from Colorado State University and B.S. degree in Electrical Engineering from Peking University. Mr. Yong Wang has 21 US patents issued and several publications including best paper rewards in conferences like EPEP and ECTC. Thomas To is a Technical Director in System Memory Signal Integrity & Device Power Group at Xilinx, Inc. Prior to joining Xilinx, Thomas was with NVIDIA Advanced Technology Group focused on high speed (32GTs) circuits & system channel designs and supported different test chips for different advanced process nodes such as 20nm SOC & 16nm FINFET process. Before NVIDIA, Thomas worked for Intel for more than 16 years covered and led many different types of system memory IO development such as Sandy Bridge Server DDR IO and covered many different system memory technology ranging from DDR1 to DDR4. Thomas received his PhD degree in Electrical Engineering from the Ohio State University in 1995 & he has over 37 patents in the fields of mixed signal IO circuits and system memory configurations as well as high speed clocking for high speed memory designs. Penglin Niu is an engineer manager at Xilinx. Her team is responsible for SI/PI modeling methodology, and product SSN and PDN analysis. She was the signal integrity lead for memory interface in Xilinx before the management position. Prior to Xilinx, she worked for Intel as signal integrity lead and package design lead. She was deeply involved in high speed DDR3/DDR3L system design and high performance CPU package design. Penglin received her Ph.D. degree from University of Illinois Urbana-Champaign, and M.S. degree from University of Missouri-Rolla. Fangyi Rao is a master engineer at Keysight Technologies. He received his Ph.D. degree in theoretical physics from Northwestern University. He joined Agilent EEsof in 2006 and works on Analog/RF and SI simulation technologies in ADS and RFDE. From 2003 to 2006 he was with Cadence Design Systems, where he developed the company's Harmonic Balance technology and perturbation analysis of nonlinear circuits. Prior to 2003 he worked in the areas of EM simulation, nonlinear device modeling, and medical imaging. Juan Wang is a Staff Signal Integrity engineer at Xilinx Inc. She has been focusing on memory interface timing analysis such as DDR4/DDR3/RLDRAM3 and corresponding lab verification. Prior to Xilinx, she worked for Juniper as signal integrity engineer for more than 5 years supporting system design 10GE/XFI/XLAUI/SFI/sGMII/rGMII/PCIE/DDR3 signal integrity modeling, simulation and measurements. Juan received her MSEE from University of Missouri-Rolla and Tsinghua University. Xi (Sean) Long is a senior Signal Integrity engineer at Xilinx Inc. His work at Xilinx focus on timing analysis and lab validation of DDR memory interface. Prior to Xilinx, he was with Nvidia Corp as a Mixed Signal Design/Validation engineer working on circuit design and lab validation of analog blocks in DDR and SERDES interfaces such as LPDDR4/GDDR5/PCIE. He received his MSEE from University Delaware |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://www.xilinx.com/publications/events/designcon/2017/characterization-ddr4-receiver-sensitivity-impact-post-equalization-eye-paper.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
