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DESIGNCON 2009 SSO Noise , Eye Margin , and Jitter Characterization for I / O Power Integrity
| Content Provider | Semantic Scholar |
|---|---|
| Author | Pandit, V. S. Chuang, Hsiao-Ching |
| Copyright Year | 2008 |
| Abstract | In this paper, we describe the Power Integrity design and characterization for a single ended I/O interface through noise, EYE margin, and jitter measurements. The frequency domain techniques are used for designing the I/O PDN. For PDN characterization, onchip PDN elements are extracted through the VNA measurements. The peak to peak voltage noise is measured on-chip at the driver. The Eye margin reduction and jitter induced due to power noise are characterized versus frequency. The overall signature of the time domain noise, Eye margin reduction and jitter response is well correlated with simulated impedance response. Author’s Biography Vishram S. Pandit: Vishram is Power Integrity Engineer at Intel Corporation. He works on developing power delivery designs for high speed interfaces. His focus areas include highspeed system power delivery, on-chip power delivery, and Signal/ Power Integrity codesign. Ashish N. Pardiwala: Ashish is Analog Design Engineer at Intel Corporation. He works on Signal Integrity Engineering characterization for high speed interfaces. His focus areas include System level Signal Integrity characterization, path-finding, and test vehicles for future technologies. Hsiao-ching Chuang: Hsiao-Ching is Analog Circuit Engineer at Intel Corporation. She works on custom logic circuits, timing analysis and specification definition for high-speed interfaces. Myoung Joon Choi: Myoung "Joon" Choi is a signal and power integrity engineer at Intel Corporation, working on signal integrity, system analysis and high speed channel optimization, and SI-PI co-Integrity. His research interests are modeling, new simulation algorithms, and high speed signal-power integrity. He has received the M.S. and PhD degree from the electrical and computer engineering at the University of Illinois at UrbanaChampaign (UIUC) in 2001 and 2004 respectively and received the B.S. degree from Korea University, Seoul, Korea, in 1997. Md. Ruhul Quddus: Ruhul is Power Integrity (power delivery network) engineer at Intel Corporation. He is responsible for computer system products power delivery network design. His focus areas include developing statistical PD methodology and jitter-based target to design PDN. 1.0 Introduction The Power Delivery Network (PDN) for a single ended Input/ Output (I/O) interface is designed. Figure 1 shows a simplified diagram for a single ended I/O interface. It is a push-pull driver with Center Tap Termination (CTT) at the receiver end. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.magazines007.com/pdf/DC09_VSPandit.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
