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DesignCon 2015 Ultrascale DDR 4 De-emphasis and CTLE Feature Optimization with Statistical Engine for BER Specification
| Content Provider | Semantic Scholar |
|---|---|
| Author | Niu, Penglin |
| Copyright Year | 2014 |
| Abstract | Effects of driver de-emphasis and receiver continuous time linear equalizer (CTLE) are investigated on a FPGA DDR4 2400Mbps memory system. Results show that de-emphasis and CTLE are effective techniques to mitigate inter-symbol-interference (ISI), increase margins and improve tolerance to driver slew rate. A highly efficient yet accurate approach is presented to calculate DQ eye opening at the extremely low bit-error-rate (BER) target of 10-16 specified in DDR4. The approach employs statistical methods to directly compute eye probability distributions and BER. ISI, crosstalk and asymmetric edges are taken into account in the calculations. Timing margins are measured for design verification and optimization. Author(s) Biography Penglin Niu is an engineer manager at Xilinx. Her team is responsible for SI/PI modeling methodology, and product SSN and PDN analysis. She was the signal integrity lead for memory interface in Xilinx before the management position. Prior to Xilinx, she worked for Intel as signal integrity lead and package design lead. She was deeply involved in high speed DDR3/DDR3L system design and high performance CPU package design. Penglin received her Ph.D. degree from University of Illinois Urbana-Champaign, and M.S. degree from University of Missouri-Rolla. Fangyi Rao is a master engineer at Keysight Technologies. He received his Ph.D. degree in theoretical physics from Northwestern University. He joined Agilent EEsof in 2006 and works on Analog/RF and SI simulation technologies in ADS and RFDE. From 2003 to 2006 he was with Cadence Design Systems, where he developed the company's Harmonic Balance technology and perturbation analysis of nonlinear circuits. Prior to 2003 he worked in the areas of EM simulation, nonlinear device modeling, and medical imaging. Juan Wang is a Staff Signal Integrity engineer at Xilinx Inc. She has been focusing on memory interface timing analysis such as DDR4/DDR3/RLDRAM3 and corresponding lab verification. Prior to Xilinx, she worked for Juniper as signal integrity engineer for more than 5 years supporting system design 10GE/XFI/XLAUI/SFI/sGMII/rGMII/PCIE/DDR3 signal integrity modeling, simulation and measurements. Juan received her MSEE from University of Missouri-Rolla and Tsinghua University. Gary Otonari is a Signal Integrity and Power Integrity engineer with 25 years of experience in high frequency and high speed hardware design. He received his BSEE from UCLA and worked at Hughes Aircraft as a satellite communications RF payload engineer. Mr. Otonari worked for EEsof Inc., GigaTest Labs and Sigrity Inc (now Cadence) in a variety of positions related to EDA, Signal Integrity and Power Integrity design. He has published numerous technical papers on measurement and simulation topics. He is currently Account Manager for Keysight Technologies in Silicon Valley. Nilesh Kamdar is District Manager, Applications Engineering, Western Region at Keysight Technologies. He has over 15 years of experience working on high frequency and high speed digital design. He has published various technical papers on Signal and Power Integrity designs. Previously, Mr. Kamdar was Senior Applications Engineer at Agilent EEsof and before that he managed the Simulation Architecture team at Agilent EEsof. He received his Masters of Science degree in Electrical Engineering from Utah State University in 1999. Yong Wang is currently Director of Engineering at Xilinx leading Device Power and Signal Integrity Group since 2011. His team owns Xilinx product families’ SI/PI methodology development, noise/timing/jitter analysis, interface timing such as DDR4/3, and corresponding verification/characterization. Prior to joining Xilinx, Mr. Yong Wang has been system design lead and SI/PI lead of several companies such as NVIDIA, MetaRAM, HP/Intel. He led the world first 16GB and 32GB R-DIMM design, validation and production with patented memory buffer ASIC design when he was system lead with MetaRAM. In NVIDIA/HP/Intel, he provided technical leadership in the areas such as but not limited to, IA-64 system front-side parallel bus channel timing, serial link channel analysis, system level power modeling, on-die power grid noise/timing analysis and timing/noise validation in the lab. Mr. Yong Wang received his M.S. degree in Electrical Engineering from Colorado State University and B.S. degree in Electrical Engineering from Peking University. Mr. Yong Wang has 21 US patents issued and several publications including best paper rewards in conferences like EPEP and ECTC. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://signal-integrity.blogs.keysight.com/wp-content/uploads/2015/02/1-WE3Paper_UltrascaleDDR4De-emphasisandCTLE.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
