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Threshold-voltage instability of polymer thin-film transistor under gate-bias and drain-bias stresses
| Content Provider | Semantic Scholar |
|---|---|
| Author | Laib, P. T. Wanga, Zhicheng Hana, J. Liaoa, R. |
| Copyright Year | 2008 |
| Abstract | Polymer thin-film transistors (PTFTs) based on MEH-PPV semiconductor are fabricated by spin-coating process and characterized. Gate-bias and drain-bias stress effects at room temperature are observed in the devices. The saturation current decreases and the threshold voltage shifts toward negative direction upon the gate-bias stress. However, the saturation current increases and the threshold voltage shifts toward positive direction upon the drain-bias stress. For variable bias stress conditions, carrier mobility is almost unchanged. The results suggest that the origin of threshold-voltage shift upon negative gate-bias stress is predominantly associated with holes trapped within the SiO2 gate dielectric or at the SiO2/Si interface due to hotcarrier emission under high gate-bias stress, while time-dependent charge trapping into the deep trap states in the channel region is responsible for the drain-bias stress effect in the PTFTs. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://hub.hku.hk/bitstream/10722/62095/1/Content.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |