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Applying 2-way Superscalar Technique to a 32-bit RISC Microprocessor
| Content Provider | Semantic Scholar |
|---|---|
| Author | Do, Quynh Ngoc Thi Hau, Hoang Nguyen Thanh |
| Copyright Year | 2013 |
| Abstract | In one-way microprocessor, the program code is executed at the maximum (ideal) rate of one instruction per cycle. In practice, due to the occurrence of branch instruction, this rate is less than 1. Superscalar architecture, when applied to a 32-bit RISC microprocessor, enables the handling of two instructions in a single machine cycle. To further increase the processing speed, the out-of-order execution is also applied to process an instruction that its operands are ready. As a result, the microprocessor which can complete two instructions per cycle is obtained. |
| Starting Page | 33 |
| Ending Page | 42 |
| Page Count | 10 |
| File Format | PDF HTM / HTML |
| DOI | 10.32508/stdj.v16i4.1582 |
| Volume Number | 16 |
| Alternate Webpage(s) | http://stdj.scienceandtechnology.com.vn/index.php/stdj/article/download/1582/1916 |
| Alternate Webpage(s) | https://doi.org/10.32508/stdj.v16i4.1582 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |