Loading...
Please wait, while we are loading the content...
Similar Documents
Design of a Tapped Delay Line Time-To-Digital Converter with 0 . 18 Μ M CMOS
| Content Provider | Semantic Scholar |
|---|---|
| Author | Wang, Wei Yuan, Jun |
| Copyright Year | 2017 |
| Abstract | This paper designed a tapped delay line Time-to-Digital Converter(TDC) based on 0.18μm CMOS, there is total level 128 voltage-controlled delay line.The symmetric delay phase-locked loop is used to increase the stability of delay chain and reduce the system clock’s skew and jitter. The simulation results show that : when the voltage is 1.8V, and the reference clock frequency is 250MHz, the least significant bit (LSB) is about 84.6 ps, the effective accuracy (RMS) is about 40.6 ps, the differential nonlinear is -0.7 LSB < DNL < 0.8 LSB, the integral nonlinear is -0.9 LSB < INL < 1.4 LSB. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ijscience.org/download/IJS-4-2-168-173.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
