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Two-Stage Clock-Free Time-to-Digital Converter Based on Vernier and Tapped Delay Lines in FPGA Device
| Content Provider | MDPI |
|---|---|
| Author | Szplet, Ryszard Czuba, Arkadiusz |
| Copyright Year | 2021 |
| Description | This article presents an idea, design and test results of a new time-to-digital converter (TDC) implemented in an FPGA device. The high resolution of 13 ps and measurement range of 3.4 ns are achieved based on a two-stage time interpolation (TI). In the first and second stages of the TI we have used the Vernier delay line and a single tapped delay line, respectively. This solution provides respectable metrological parameters without the need to use a clock signal, and significantly saves the logical resources of an integrated circuit (IC). The proposed method, generally based on two different variants of the discrete delay line, is easy to design and implement in digital ICs. For experimental verification, the TDC was implemented in a single programmable device from family Virtex-7 (Xilinx). |
| Starting Page | 2190 |
| e-ISSN | 20799292 |
| DOI | 10.3390/electronics10182190 |
| Journal | Electronics |
| Issue Number | 18 |
| Volume Number | 10 |
| Language | English |
| Publisher | MDPI |
| Publisher Date | 2021-09-07 |
| Access Restriction | Open |
| Subject Keyword | Electronics Time-to-digital Converter Time Interpolation Tapped Delay Line Fpga Precise Time Metrology |
| Content Type | Text |
| Resource Type | Article |
