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Design and Implementation of Low Power and High Performance 0 . 13 μ m CMOS Dynamic Comparator for Analog to Digital Converter
| Content Provider | Semantic Scholar |
|---|---|
| Author | Akanksha Vashishtha, Jaya Nidhi |
| Copyright Year | 2014 |
| Abstract | The proposed design is a CMOS dynamic comparator using dual input double output differential amplifier as latch stage suitable for high speed analog-to-digital converters with low power dissipation and high performance. The design's output shows lower power dissipation and higher speed than the other latch type voltage sense comparator. The proposed dynamic comparator topology is based on positive feedback where two cross coupled differential pair and two switchable current sources are used. The circuit is designed using 0.13 μm CMOS technology and the desired output obtained with 20 MHz clock frequency and 3.3V power supply. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ijsret.org/pdf/120895.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |