Loading...
Please wait, while we are loading the content...
Similar Documents
A Single-Chip CMOS Digitally Synthesized 0-35 MHz Agile Function Generator
| Content Provider | Semantic Scholar |
|---|---|
| Author | Meenakarn, Charan Thanachayanont, Apinunt |
| Copyright Year | 2002 |
| Abstract | This paper describes the design and implementation of a single-chip digitally synthesized 0-35 MHz agile function generator. The chip comprises an integrated direct digital synthesizer (DDS) with a 10-bit onchip digital-to-analog converter (DAC) using an n-well single-poly triple-metal 0.5-μm CMOS technology. The main features of the chip include maximum clock frequency of 100 MHz at 3.3-V supply voltage, 32-bit frequency tuning word resolution, 12-bit phase tuning word resolution, and an on-chip 10-bit DAC. The chip provides sinusoidal, ramp, saw-tooth, and random waveforms with phase and frequency modulation, and power-down function. At 100-MHz clock frequency, the chip covers a bandwidth from dc to 35 MHz in 0.0233-Hz frequency steps with 190-ns frequency switching speed. The complete chip occupies 12-mm die area and dissipates 0.4 W at 100MHz clock frequency. |
| Starting Page | 1985 |
| Ending Page | 1988 |
| Page Count | 4 |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.kmutt.ac.th/itc2002/CD/pdf/19_07_45/FA2_PI/1.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
