NDLI: A 225 MHz resonant clocked ASIC chip

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A 225 MHz resonant clocked ASIC chip

Content Provider	ACM Digital Library
Author	Sathe, Visvesh S. Kim, Joohee Ziesler, Conrad H. Papaefthymiou, Marios C.
Abstract	We have recently designed, fabricated, and successfully tested an experimental chip that validates a novel method for reducing clock dissipation through energy recovery. Our approach includes a single-phase sinusoidal clock signal, an L-C resonant sinusoidal clock generator, and an energy recovering flip-flop. Our chip comprises a dual-mode ASIC with two independent clock systems, one conventional and one energy recovering, and was fabricated in a micron bulk CMOS process. The ASIC computes a pipelined discrete wavelet transform with self-test and contains over 3500 gates. We have verified correct functionality and obtained power measurements in both modes of operation for frequencies up to 225MHz. In the energy recovering mode, our power measurements account for all of the dissipation factors, including the operation of the integrated resonant clock generator, and show a net energy savings over the conventional mode of operation. For example, at 115MHz, measured dissipation is between 60% and 75% of the conventional mode, depending on primary input activity. To our knowledge, this is the first ever published account of a direct experimentally-measured comparison between a complete energy recovering ASIC chip and its conventional implementation correctly operating in silicon at frequencies exceeding 100MHz.
Starting Page	48
Ending Page	53
Page Count	6
File Format	PDF
ISBN	158113682X
DOI	10.1145/871506.871523
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2003-08-25
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Low energy Clock generator Resonant lc tank Vlsi Single phase Flip-flop Cmos Adiabatic logic
Content Type	Text
Resource Type	Article

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