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Investigation of a solder bumping technique for flip‐chip interconnection
| Content Provider | Semantic Scholar |
|---|---|
| Author | Hutt, David A. Rhodes, Daniel Conway, Paul P. Mannan, Samjid H. Whalley, D. C. Holmes, Andrew S. |
| Copyright Year | 2000 |
| Abstract | As the demand for flip‐chip products increases, the need for low cost high volume manufacturing processes also increases. Currently solder paste printing is the wafer bumping method of choice for device pitches down to 150‐200μm. However, limitations in print quality and stencil manufacture mean that this technology is not likely to move significantly below this pitch and new methods will be required to meet the demands predicted by the technology roadmaps. This paper describes experiments conducted on carriers made from silicon for bumping of die using solder paste. An anisotropic etching process was used to generate pockets in the silicon surface into which solder paste was printed. Die were then placed against the carrier and reflowed to transfer the solder directly to the bondpads. An assessment was carried out of the potential application and limitations of this technique for device pitches at 225 and 127μm. |
| Starting Page | 7 |
| Ending Page | 14 |
| Page Count | 8 |
| File Format | PDF HTM / HTML |
| DOI | 10.1108/09540910010312366 |
| Volume Number | 12 |
| Alternate Webpage(s) | https://dspace.lboro.ac.uk/dspace-jspui/bitstream/2134/3927/1/RC42.pdf |
| Alternate Webpage(s) | https://doi.org/10.1108/09540910010312366 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
