SCR device with dynamic holding voltage for on-chip ESD protection in a 0.25-/spl mu/m fully salicided CMOS process

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SCR Device With Dynamic Holding Voltage for On-Chip ESD Protection in a 0.25- m Fully

Substrate-triggered technique for on-chip ESD protection design in a 0.18-/spl mu/m salicided CMOS process

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ESD implantations for on-chip ESD protection with layout consideration in 0.18-/spl mu/m salicided CMOS technology

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Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-/spl mu/m CMOS process

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ESD implantations in 0.18-/spl mu/m salicided CMOS technology for on-chip ESD protection with layout consideration

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MOS-bounded diodes for on-chip ESD protection in a 0.15-/spl mu/m shallow-trench-isolation salicided CMOS process

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Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-/spl mu/m salicided CMOS process

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Substrate-triggered technique for on-chip ESD protection design in a 0.18-/spl mu/m salicided CMOS process

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