NDLI: ESD implantations in 0.18-/spl mu/m salicided CMOS technology for on-chip ESD protection with layout consideration

Content Provider	IEEE Xplore Digital Library
Author	Ming-Dou Ker Che-Hao Chuang
Copyright Year	2001
Description	Author affiliation: Integrated Circuits & Syst. Lab., Nat. Chiao Tung Univ., Hsinchu, Taiwan (Ming-Dou Ker)
Abstract	ESD robustness of CMOS devices used in the I/O pad is a major reliability issue as the diffusion junction depth is reduced and LDD (lightly-doped drain)/salicide structures are generally used in sub-quarter-micron CMOS technology. In order to enhance ESD robustness, some ESD implantations have been reported for inclusion into the process flow to modify the device structures for ESD protection (Lee, 1997; Hsue and Ko, 1994; Lowrey and Chance, 1996; Yang, 2000). In this paper, the effectiveness of different ESD implantation solutions on NMOS and diode devices for ESD protection is investigated in a 0.18 /spl mu/m salicided bulk CMOS process. The second breakdown current (It2) of the fabricated devices is measured by the transmission line pulse generator (TLPG). The human-body-model (HBM) and the machine-model (MM) ESD levels of these devices are also measured and compared. The layout dependence of NMOS devices and diodes with different ESD implantations are also investigated.
Sponsorship	IEEE Electron Device Soc
Starting Page	85
Ending Page	90
File Size	529968
Page Count	6
File Format	PDF
ISBN	0780366751
DOI	10.1109/IPFA.2001.941461
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-07-13
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology Electrostatic discharge Robustness Protection MOS devices Diodes Transmission line measurements CMOS process Electric breakdown Current measurement
Content Type	Text
Resource Type	Article

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