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Channel Analysis for a 6.4 Gb s−1 DDR5 Data Buffer Receiver Front-End
| Content Provider | Scilit |
|---|---|
| Author | Lehmann, Stefanie Gerfers, Friedel |
| Copyright Year | 2017 |
| Description | In this contribution, the channel characteristic of the next generation DDR5-SDRAM architecture and possible approaches to overcome channel impairments are analysed. Because modern enterprise server applications and networks demand higher memory bandwidth, throughput and capacity, the DDR5-SDRAM specification is currently under development as a follow-up of DDR4-SDRAM technology. In this specification, the data rate is doubled to DDR5-6400 per IO as compared to the former DDR4-3200 architecture, resulting in a total per DIMM data rate of up to 409.6 Gb s−1. The single-ended multi-point-to-point CPU channel architecture in DDRX technology remains the same for DDR5 systems. At the specified target data rate, insertion loss, reflections, cross-talk as well as power supply noise become more severe and have to be considered. Using the data buffer receiver front-end of a load-reduced memory module, sophisticated equalisation techniques can be applied to ensure target BER at the increased data rate. In this work, the worst case CPU back-plane channel is analysed to derive requirements for receiver-side equalisation from the channel response characteristics. First, channel impairments such as inter-symbol-interference, reflections from the multi-point channel structure, and crosstalk from neighboring lines are analysed in detail. Based on these results, different correction methods for DDR5 data buffer front-ends are discussed. An architecture with 1-tap FFE in combination with a multi-tap DFE is proposed. Simulation of the architecture using a random input data stream is used to reveal the required DFE tap filter depth to effectively eliminate the dominant ISI and reflection based error components. |
| Ending Page | 161 |
| Page Count | 5 |
| Starting Page | 157 |
| e-ISSN | 16849973 |
| DOI | 10.5194/ars-15-157-2017 |
| Journal | Advances in Radio Science |
| Volume Number | 15 |
| Language | English |
| Publisher | Copernicus GmbH |
| Publisher Date | 2017-09-21 |
| Access Restriction | Open |
| Subject Keyword | Front End Multi Point Receiver Front Ddr5 Data Buffer Buffer Receiver |
| Content Type | Text |
| Resource Type | Article |
