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A 5 Gb / s Optical Receiver Front-End in 0 . 18 m CMOS Technology
| Content Provider | Semantic Scholar |
|---|---|
| Author | Yuan-Jun, Liang Lingzhi, Ke |
| Copyright Year | 2009 |
| Abstract | A 5Gb/s optical receiver front-end for optical interconnection is presented in this paper. A transimpedance amplifier (TIA), limiting amplifiers (LA), output buffer and a bias circuit are integrated in deep Nwell 0.18 m CMOS technology. As the input current amplitude is 30 A, the differential output voltage is achieved to be 124 mV. The linear gain is 78.8dB and consumes 200mW under 1.8V supply. Without on-chip inductor, the core size of the circuit is only 800 300 m. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.academypublisher.com/proc/iwisa09/papers/iwisa09p481.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
