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Inductorless CMOS Receiver Front-End Circuits for 10-Gb/s Optical Communications
| Content Provider | Semantic Scholar |
|---|---|
| Author | Chen, Hsin-Liang Chen, Chih-Hao Yang, Wei-Bin Chiang, Jen-Shiun |
| Copyright Year | 2009 |
| Abstract | In this paper, a 10-Gb/s inductorless CMOS receiver front end is presented, including a transimpedance amplifier and a limiting amplifier. The transimpedance amplifier incorporates Regulated Cascode (RGC), active-inductor peaking, and intersecting active feedback circuits to achieve a transimpedance gain of 56 dBΩand a bandwidth of 8.27 GHz with a power dissipation of 35 mW. The limiting amplifier employs interleaving active feedback to achieve a differential voltage gain of 44.5 dB and a bandwidth of 10.3 GHz while consuming 226 mW. Both circuits are realized in 0.18-μm CMOS technology with a 1.8-V supply. |
| Starting Page | 449 |
| Ending Page | 458 |
| Page Count | 10 |
| File Format | PDF HTM / HTML |
| DOI | 10.6180/jase.2009.12.4.09 |
| Volume Number | 12 |
| Alternate Webpage(s) | http://www2.tku.edu.tw/~tkjse/12-4/09-EE9715.pdf |
| Alternate Webpage(s) | https://doi.org/10.6180/jase.2009.12.4.09 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
