NDLI: Nanoscale field effect diode (FED) with improved speed and I ON/I OFF ratio

Content Provider	IET Digital Library
Author	Rezaei, Arash Ganji, Bahram Azizollah Gholipour, Morteza
Abstract	Field effect diodes (FEDs) are devices that have higher ON current and lower OFF current compared to metal oxide semiconductor field effect transistors in similar dimensions. The modified FED and side contacted FED (S-FED) structures do not turn off for 40 nm channel lengths and shorter by considering the band-to-band tunnelling model. In this study, a new structure of FED with a 25 nm channel is presented. In this structure, the use of isolating oxides and reservoirs in the channel causes improvement in the structural compared to the conventional FED structures. The proposed techniques reduce the tunnelling in the channel. The simulations have been done by using Silvaco TCAD. In the proposed structure, the results show that the OFF current and gate delay are decreased from 1.5 mA to 66.5 nA and 0.103 to 0.033 ps, respectively. Also, compared with the S-FED structure by considering the band-to-band tunnelling model, the knee voltage for the length of the 25 nm channel dropped from 0.8 to 0.4 volts. Furthermore, the I ON/I OFF ratio, which is an important parameter in digital applications, dramatically increases to a magnitude of 105.
Starting Page	309
Ending Page	313
Page Count	5
ISSN	1751858X
Volume Number	13
e-ISSN	17518598
Issue Number	Issue 3, May (2019)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/13/3
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.5210
Journal	IET Circuits, Devices & Systems
Publisher Date	2018-12-03
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Band-to-band Tunnelling Model Channel Lengths Conventional FED Structures Current 66.5 NA to 1.5 MA Gate Delay Junction And Barrier Diode Knee Voltage Metal Oxide Semiconductor Field Effect Transistors Modified FED Structure Nanoelectronics Nanoscale Field Effect Diode Reservoirs S-FED Structure Semiconductor Diode Side Contacted FED Structure Silvaco TCAD Size 25.0 Nm Size 40.0 Nm Time 0.033 Ps to 0.103 Ps Tunnelling Voltage 0.8 V to 0.4 V
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Ultrathin-body tunnelling FET using a trench structure

Analysis of interface trap charges on performance variation in L-shaped tunnel field-effect transistor

Improved nanoscale field effect diode

Approach to suppress ambipolar conduction in Tunnel FET using dielectric pocket

Performance Assessment of Nanoscale Field-Effect Diodes

Physical insight and performance metrics of monolayer MX2 heterojunction TFETs

Ultra-low leakage SRAM design with sub-32 nm tunnel FETs for low standby power applications

Analysis of GaN nanoscale FinFET for low power circuit applications

Optimum current-voltage characteristics of GaAs/AlAs intraband microwave devices

Nanoscale field effect diode (FED) with improved speed and I ON/I OFF ratio

Similar Documents

Ultrathin-body tunnelling FET using a trench structure

Analysis of interface trap charges on performance variation in L-shaped tunnel field-effect transistor

Improved nanoscale field effect diode

Approach to suppress ambipolar conduction in Tunnel FET using dielectric pocket

Performance Assessment of Nanoscale Field-Effect Diodes

Physical insight and performance metrics of monolayer MX2 heterojunction TFETs

Ultra-low leakage SRAM design with sub-32 nm tunnel FETs for low standby power applications

Analysis of GaN nanoscale FinFET for low power circuit applications

Optimum current-voltage characteristics of GaAs/AlAs intraband microwave devices

Nanoscale field effect diode (FED) with improved speed and I ON/I OFF ratio