NDLI: Modified X–Y routing for mesh topology based NoC router on field programmable gate array

Content Provider	IET Digital Library
Author	Shahane, Priti Pisharoty, Narayan
Abstract	Network on chip (NoC) has been proposed as an enormously scalable solution to address communication problems in system on chip (SoC). The interconnections among multiple cores/multiple Intellectual Property modules on a chip have a major impact on communication and performance of the chip design in terms of area, throughput, latency and power. Hence, an efficient design of the NoC interconnect is of paramount importance. In this study, a novel idea of the NoC router using a single-side buffer in the input block and a programmable priority encoder in the scheduler is discussed and a 4 × 4 mesh topology based router design is implemented on a field programmable gate array device using these blocks. This gives an area optimisation of the router due to the use of a small buffer. Furthermore, a modified X–Y routing algorithm is discussed and implemented for the 8 × 8 mesh topology-based router. The result shows that the modified X–Y routing algorithm requires only two hops to reach any source destination pair resulting in latency optimisation of the NoC router. Thus, the router design with a single buffer and a modified X–Y routing algorithm provides the best solution for area and latency optimisation.
Starting Page	391
Ending Page	398
Page Count	8
ISSN	1751858X
Volume Number	13
e-ISSN	17518598
Issue Number	Issue 3, May (2019)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/13/3
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.5356
Journal	IET Circuits, Devices & Systems
Publisher Date	2019-01-07
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Area Optimisation Digital Circuit Design, Modelling And Testing Electrical/electronic Equipment Energy Utilisation Field Programmable Gate Array Field-programmable Gate Array Device Integrated Circuit Interconnections Interconnection Architectures ISLIP Scheduler Latency Optimisation Logic And Switching Circuit Logic Circuit Low Power Consumption Low Power Electronics Mesh Topology-based NoC Router Mesh Topology-based Router Design Metallisation And Interconnection Technology Modified X–Y Routing Algorithm Multiple Cores Network on Chip Network Routing Network-on-chip NoC Interconnect Performance On-chip Interconnect Programmable Priority Encoder Single-side Buffer SoC Source Destination Pair System on Chip
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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