NDLI: Optimisation of test architecture in three-dimensional stacked integrated circuits for partial stack/complete stack using hard system-on-chips

Content Provider	IET Digital Library
Author	Roy, Surajit Kumar Giri, Chandan Rahaman, Hafizur
Abstract	Three-dimensional stacked integrated circuits (3D SICs) are currently evolving as an area of great interest in modern semiconductor industry. Several partial stack tests are required during three-dimensional assembly because the die stacking steps and bonding may introduce defects. In this study, the authors have addressed test architecture optimisation for 3D SICs implemented with hard dies under through-silicon-via constraints. The main objective of their algorithm is to minimise test time either for testing of a complete stack or complete stack and several partial stacks. Experimental results are performed for three different handcrafted 3D SICs comprising several system-on-chips (SOCs) from International Test Conference 2002 (ITC'02) SOC test benchmarks. In this study, they have considered that the die level test architecture is fixed and each die consists of one SOC. The test length for multiple test insertions as well as the final complete stack are also shown.
Starting Page	268
Ending Page	274
Page Count	7
ISSN	17518601
Volume Number	9
e-ISSN	1751861X
Issue Number	Issue 5, Sep (2015)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cdt/9/5
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2014.0137
Journal	IET Computers & Digital Techniques
Publisher Date	2015-03-31
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	3D SIC Complete Stack Design And Testing Die Level Test Architecture Die Stacking Steps Equivalent Circuit Partial Stack Semiconductor Device Modelling Semiconductor Device Testing Semiconductor Industry Semiconductor Integrated Circuit SOC System-on-chip Test Architecture Optimisation Test Insertions Three-dimensional Assembly Three-dimensional Integrated Circuit Three-dimensional Stacked Integrated Circuit Through-silicon-via Constraint
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Software

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