NDLI: Efficient implementation of bit-parallel fault tolerant polynomial basis multiplication and squaring over GF(2 m )

Content Provider	IET Digital Library
Author	Rashidi, Bahram Sayedi, Sayed Masoud Farashahi, Reza Rezaeian
Abstract	This study presents the design and implementation of an efficient structure for fault tolerant bit-parallel polynomial basis multiplication and squaring over GF(2 m ), based on a similar strategy of Roving method with a minimum overhead. The Roving method is an efficient method for the circuits in which many similar and independent structures exist. The architectures of the polynomial basis multiplication and squaring over binary finite fields have inherent regularity in their subsections of the structures. Therefore, they are compatible to the applied version of Roving fault tolerant method. To generalise the proposed architecture, the multiplication and squaring operations are examined for different primitive polynomial, including general irreducible polynomials, irreducible pentanomials and irreducible trinomials. In the proposed design, the extracted common circuit has low hardware utilisation compared with that of the main circuit. The fault tolerant circuit is constructed by using three copies of the common circuit, a comparator and a voter circuit. The comparator and voter have parallel architectures with low critical path delays, which is a critical factor in any highly computational system. The design has been successfully verified and synthesised onVirtex-4 XC4VLX200 FPGA using Xilinx ISE 11. The results show an overall improvement in the speed and hardware usage compared with those of previous designs.
Starting Page	18
Ending Page	29
Page Count	12
ISSN	17518601
Volume Number	10
e-ISSN	1751861X
Issue Number	Issue 1, Jan (2016)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cdt/10/1
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2015.0020
Journal	IET Computers & Digital Techniques
Publisher Date	2016-01-01
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Algebra Binary Finite Field Bit-parallel Fault Tolerant Polynomial Basis Multiplication Bit-parallel Fault Tolerant Polynomial Basis Squaring Code Common Circuit Comparator Digital Circuit Design, Modelling And Testing Fault Tolerant Circuit Fault Tolerant Computing Field Programmable Gate Array Galois Field General Irreducible Polynomials GF(2m) Independent Structure Irreducible Pentanomials Irreducible Trinomials Logic And Switching Circuit Logic Circuit Logic Design Method Low Critical Path Delay Multiplying Circuit Parallel Architecture Performance Evaluation And Testing Polynomial Primitive Polynomial Roving Fault Tolerant Method Virtex-4 XC4VLX200 FPGA Voter Circuit Xilinx ISE 11
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Software

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