NDLI: Sensitivity analysis of testability parameters for secure IC design

Content Provider	IET Digital Library
Author	Rajendran, Sreeja Regeena, Mary Lourde
Abstract	Insertion of malicious circuits commonly known as Hardware Trojans into an original integrated circuit (IC) design to alter the functionality has been a major concern in recent years. As a result, over the years multiple techniques have been suggested by researchers to combat these malicious threats. Hard to test nets in any logic circuit are the most vulnerable to insertion of Hardware Trojans. Testability analysis is the process of identification of these hard to test nets in a logic circuit. Testability analysis is achieved through the testability metrics namely controllability and observability. Testability metrics can be used as a yardstick in devising efficient Hardware Trojan detection methods. The crux of this study is a novel method for identification of susceptible nets that are prone to Hardware Trojan insertions in a logic circuit. The study also presents a comprehensive analysis of the impact on testability parameters as a result of Hardware Trojans in the identified susceptible nets. The method utilises the testability parameters of nets to define threshold values for isolating susceptible nets in a design. The study details out the impact of the number of trigger inputs as well as the distribution of trigger nets on the testability metrics of digital circuits.
Starting Page	158
Ending Page	165
Page Count	8
ISSN	17518601
Volume Number	14
e-ISSN	1751861X
Issue Number	Issue 4, Jul (2020)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cdt/14/4
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2019.0217
Journal	IET Computers & Digital Techniques
Publisher Date	2020-03-19
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Data Security Digital Circuit Efficient Hardware Trojan Detection Method Hardware Trojan Insertions Identified Susceptible Nets Integrated Circuit Design Invasive Software Logic And Switching Circuit Logic Circuit Malicious Circuit Malicious Threats Original Integrated Circuit Design Secure IC Design Sensitivity Analysis Testability Analysis Testability Metrics Testability Parameter Trigger Nets Years Multiple Technique
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Software

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