NDLI: 3–10 GHz noise-cancelling CMOS LNA using g m -boosting technique

Content Provider	IET Digital Library
Author	Lee, Muyeon Kwon, Ickjin
Abstract	An ultra-wideband (UWB) low-noise amplifier (LNA) using a 0.11 µm CMOS technology is proposed. The common-gate (CG) input stage for wideband input impedance matching and the common-source (CS) stage for noise cancelling are applied. In the proposed LNA, the current of the CG input stage can be significantly reduced by applying the gm -boosting technique using the noise-cancelling CS stage without additional amplifier, and the noise performance can be improved at the same power consumption. For low-power operation, the LNA consumes 2.9 mW and achieves a noise figure (NF) of S 21 between 16.5 and 17.6 dB at S 11, lower than −12.4 and 3.6–3.7 dB at frequencies of 3–10 GHz. In low-noise operation, the LNA consumes 8.3 mW, achieving S 11 of less than −10.7 dB, S 21 of 17.5–18.7 dB, and NF of 2.4–2.9 dB.
Starting Page	12
Ending Page	16
Page Count	5
ISSN	1751858X
Volume Number	12
e-ISSN	17518598
Issue Number	Issue 1, Jan (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/12/1
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0094
Journal	IET Circuits, Devices & Systems
Publisher Date	2017-09-04
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Amplifiers CMOS Analogue Integrated Circuit CMOS Integrated Circuit Common-gate Input Stage Common-source Stage Electromagnetic Compatibility Field Effect MMIC Frequency 3 GHz to 10 GHz Gm-boosting Technique Impedance Matching Interference Interference Suppression Low Noise Amplifier Low Power Electronics Microwave IC MMIC Amplifiers Noise Figure 16.5 DB to 17.6 DB Noise Figure 2.4 DB to 2.9 DB Noise Performance Noise-cancelling CMOS LNA Power 2.9 MW Power 8.3 MW Power Consumption Size 0.11 Mum Ultra Wideband Technology Ultra-wideband Low-noise Amplifier UWB LNA Wideband Input Impedance Matching
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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