NDLI: Area-efficient parallel adder with faithful approximation for image and signal processing applications

Content Provider	IET Digital Library
Author	Palanisamy, Gnanambikai Natarajan, Vijeyakumar Krishnasamy Sundaram, Kalaiselvi
Abstract	Design of low-power and area-efficient portable complementary metal–oxide–semiconductor processors for image and signal processing applications demand reduction in transistor switching and count. Adder is the fundamental block of all arithmetic operations performed in processing units. In this study, an error-tolerant parallel adder with faithful approximation is proposed that can optimise area and accuracy. In the proposed parallel adder, for n bit input and m bit adder block, least n/2m blocks are designed with approximate logic using carry by-pass addition algorithm and most n/2m blocks are designed with exact logic using carry select addition algorithm. Least significant approximate part of the adder is designed with either exact full adder (EFA) or fault-tolerant full adder (FTFA) cells. This confines the maximum error in the proposed-EFA and proposed-FTFA designs to be not more than unit bit value with weights 2[(n/2m)−1]m and 2 n /2, respectively. Two different FTFA cells are proposed and implemented in the approximate blocks. The synthesis results of the proposed-EFA, proposed-FTFA1 and proposed-FTFA2 designs using Cadence Encounter with 90 nm ASIC technology for n = 16, m = 4 demonstrated an area saving of 22.3, 28.2 and 35%, respectively, when compared to the conventional counterpart.
Starting Page	2587
Ending Page	2594
Page Count	8
ISSN	17519659
Volume Number	13
e-ISSN	17519667
Issue Number	Issue 13, Nov (2019)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-ipr/13/13
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-ipr.2019.0580
Journal	IET Image Processing
Publisher Date	2019-09-04
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Adder Approximate Blocks Approximate Logic Approximation Theory Area-efficient Parallel Adder Area-efficient Portable Complementary Metal–oxide–semiconductor Processor Design Arithmetic Operations ASIC Technology Cadence Encounter Carry By-pass Addition Algorithm Carry Select Addition Algorithm CMOS Logic Circuit Digital Circuit Design, Modelling And Testing EFA Error-tolerant Parallel Adder Cell Exact Full Adder Exact Logic Faithful Approximation FTFA Cell FTFA Designs Image Processing Application Interpolation And Function Approximation Least N-2m Blocks Least Significant Approximate Part Logic And Switching Circuit Logic Circuit Logic Design Method Low Power Electronics Low-power Complementary Metal–oxide–semiconductor Processor Design M Bit Adder Block N Bit Input Numerical Analysis Signal Processing Application Demand Reduction Size 90 Nm Transistor Switching Unit Bit Value
Content Type	Text
Resource Type	Article
Subject	Signal Processing Electrical and Electronic Engineering Computer Vision and Pattern Recognition Software

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