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| Content Provider | IET Digital Library |
|---|---|
| Author | Jeong, S. Lee, E. Yim, M. Yoon, G. |
| Abstract | A few-layer-thick epitaxial graphene synthesised on both the up-side and the down-side surfaces of SiC wafers in an ultra-high vacuum annealing furnace is presented. The graphene grown on the down-side surfaces of the SiC wafers that contacted with a graphite pedestal resulted in a relatively lower sheet resistance along with less graphene layers, as compared with that of their up-side surfaces. Overall, the sheet resistance of the few-layer-thick graphene grown on the down-side was found to range from 200 to 3 Ω/□, depending on the annealing time. |
| Starting Page | 98 |
| Ending Page | 100 |
| Page Count | 3 |
| ISSN | 00135194 |
| Volume Number | 50 |
| e-ISSN | 1350911X |
| Issue Number | Issue 2, Jan (2014) |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/el/50/2 |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/10.1049/el.2013.3391 |
| Journal | Electronics Letters |
| Access Restriction | Open |
| Rights Holder | © The Institution of Engineering and Technology |
| Subject Keyword | Annealing Processes Annealing Processes in Semiconductor Technology Carbon Nanotubes And Related Materials Down-side Surfaces Electric Resistance Electrical Property of Fullerenes And Related Materials Engineering Material Science Epitaxial Graphene Layer Fullerenes Graphene Semiconductor Epitaxial Layer Sheet Resistance SiC SiC Substrates Silicon Compound Substrate-Down Configuration Thin Film/low-dimensional Structure Ultra-high Vacuum Annealing Furnace Up-side SurFace |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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