NDLI: Digital PLL-based frequency synthesis: effect of loop filter shape on required DCO frequency resolution

Content Provider	IET Digital Library
Author	Verheyen, K. Torfs, G. Bauwelinck, J.
Abstract	In digital phase-locked loops (PLLs), the finite resolution of digital representation (quantisation) could pose problems, including jitter peaking and limit-cycle behaviour; both could ruin the frequency stability of a PLL. The resolution of the digitally controlled oscillator (DCO) in the PLL is limited by the smallest dimension available in a given process technology. Currently, one resorts to exhaustive time-domain simulations to ensure correct operation of a PLL. Using a behavioural model of a PLL as verification, how to choose the DCO resolution without resorting to time-domain simulations is investigated. The conditions on signal statistics for correct behaviour are repeated and the analysis to estimate the required resolution is provided. As it turns out, the root-mean-square value of the frequency deviation – neglecting quantisation – is the coarsest possible DCO resolution. One can estimate this value accurately by the integration of its power-spectral density, derived from the well-known phase-domain model of a PLL.
Starting Page	1425
Ending Page	1427
Page Count	3
ISSN	00135194
Volume Number	50
e-ISSN	1350911X
Issue Number	Issue 20, Sep (2014)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/50/20
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2014.1804
Journal	Electronics Letters
Publisher Date	2014-09-11
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	DCO Frequency Resolution Demodulator Digital Circuit Digital Phase Locked Loops Digital Phase-locked Loops Digital PLL-based Frequency Synthesis Digitally Controlled Oscillator Discriminators And Mixers Exhaustive Time-domain Simulations Finite Digital Representation Resolution Frequency Deviation Frequency Stability Frequency Synthesizers Jitter Peaking Limit-cycle Behaviour Loop Filter Shape Effect Mathematical Analysis Modulator Oscillator Phase-domain Model PLL Behavioural Model Power-spectral Density PSD Root-mean-square Value Signal Statistic Condition Time Domain Analysis
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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