NDLI: Observer-Controller Digital PLL

Content Provider	IEEE Xplore Digital Library
Author	Won Namgoong
Copyright Year	2004
Abstract	A digital phase-locked loop (DPLL) has been recently developed to exploit the increasing transistor speed of modern process technology. By employing a digitally controlled oscillator (DCO) and a time-to-digital converter (TDC), the loop filter of a DPLL becomes all-digital. Instead of designing the loop filter by digitizing a continuous-time loop response as has been commonly done, more sophisticated control schemes can be employed. In this paper, we propose to design the feedback loop in the time-domain by first modeling the DCO and TDC as a noisy ¿plant¿ in state-space form. Based on a Kalman observer of the ¿plant,¿ the proposed approach then generates optimal control signals that accurately account for the additive noise as well as the transport delay in the digital feedback system. The proposed observer-controller loop filter achieves rapid transient response time and significantly reduces the steady-state phase noise jitter compared to the conventional DPLL. Furthermore, the proposed approach enables modeling of other noise sources such as due to oscillator pulling, which is a common problem in many modern transceivers. By employing the observer-controller loop filter, the effect of oscillator pulling can be effectively removed without degrading the overall phase noise performance.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	631
Ending Page	641
Page Count	11
File Size	780615
File Format	PDF
ISSN	15498328
Volume Number	57
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase locked loops Oscillators Phase noise Digital control Digital filters Feedback loop Time domain analysis Kalman filters Signal generators Optimal control time-to-digital converter (TDC) Digital phase-locked loop (DPLL) digitally controlled oscillator (DCO) Kalman filter oscillator pulling
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Flicker Noise in Observer-Controller Digital PLL

Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops

A Digital Phase-Locked Loop With Calibrated Coarse and Stochastic Fine TDC

A Digital PLL With a Stochastic Time-to-Digital Converter

A PVT Tolerant 10 to 500 MHz All-Digital Phase-Locked Loop With Coupled TDC and DCO

A 2.8–3.2-GHz Fractional- $N$ Digital PLL With ADC-Assisted TDC and Inductively Coupled Fine-Tuning DCO

State-of-the-Art and Future Directions of High-Performance All-Digital Frequency Synthesis in Nanometer CMOS

A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function

A 1.9-GHz Fractional-N Digital PLL With Subexponent $ DeltaSigma$ TDC and IIR-Based Noise Cancellation

Observer-Controller Digital PLL

Similar Documents

Flicker Noise in Observer-Controller Digital PLL

Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops

A Digital Phase-Locked Loop With Calibrated Coarse and Stochastic Fine TDC

A Digital PLL With a Stochastic Time-to-Digital Converter

A PVT Tolerant 10 to 500 MHz All-Digital Phase-Locked Loop With Coupled TDC and DCO

A 2.8–3.2-GHz Fractional- $N$ Digital PLL With ADC-Assisted TDC and Inductively Coupled Fine-Tuning DCO

State-of-the-Art and Future Directions of High-Performance All-Digital Frequency Synthesis in Nanometer CMOS

A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function

A 1.9-GHz Fractional-N Digital PLL With Subexponent $ DeltaSigma$ TDC and IIR-Based Noise Cancellation

Observer-Controller Digital PLL