NDLI: Fully integrated four-input combining receiver front-end circuit for laser radar with static unitary detector

Content Provider	IET Digital Library
Author	Lee, Eun Gyu An, Jongsun Kim, Choul Young
Abstract	A fully integrated four-input combining receiver front-end circuit is designed in a 0.18 μm CMOS technology for laser radar with a static unitary detector (STUD). This circuit consists of four independent transimpedance amplifiers, one signal combiner, a balun and an output buffer in one single integrated chip. The circuit provides 16.2 mW power consumption for a 1.8 V supplied voltage and 59.8 dBΩ transimpedance gain in the implemented experimental prototype for electrical pulse measurement. The fabricated prototype is worked exactly the same as the operation principle of the STUD in the two-dimensional optical pulse scanning measurement. Therefore, the proposed circuit is available for the STUD-based laser detection and ranging (LADAR) system as one integrated chip. This is the first demonstrated IC for the STUD-based laser radar system.
Starting Page	1543
Ending Page	1545
Page Count	3
ISSN	00135194
Volume Number	50
e-ISSN	1350911X
Issue Number	Issue 21, Oct (2014)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/50/21
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2014.1929
Journal	Electronics Letters
Publisher Date	2014-10-06
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	2D Optical Pulse Scanning Measurement Amplifiers Balun Baluns Buffer Circuit CMOS Integrated Circuit CMOS Technology Electrical Pulse Measurement Four-input Combining Receiver Front-end Circuit Integrated Chip LADAR System Operational Amplifier Optical Radar Output Buffer Power 16.2 MW Power Consumption Pulse Measurement Radar Receiver Size 0.18 Mum Static Unitary Detector STUD-based Laser Detection And Ranging System STUD-based Laser Radar System TIA Transimpedance Amplifier Transimpedance Gain Two-dimensional Optical Pulse Scanning Measurement Voltage 1.8 V
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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