NDLI: Ultra-low-cost colour demosaicking VLSI design for real-time video applications

Content Provider	IET Digital Library
Author	Chen, Shih Lun Chang, Huan Rui Lin, Ting Lan
Abstract	A novel low-complexity and high-quality colour demosaicking algorithm is proposed for very large-scale integration (VLSI) implementation for real-time video applications. It consists of a boundary detector, a boundary mirror model and five green and red–blue colour interpolation models. Two of the five interpolation models can be selected adaptively according to boundary and position information. In addition, a boundary mirror machine and identical direction technique were used to improve the qualities of the reconstructed images. To reduce the hardware cost, memory requirement and power consumption, a hardware-sharing technique and register bank design were used to realise the proposed algorithm. The VLSI architecture of this work contains only 2.9 K gate counts and its core area is 35 966 μm2 synthesised by a 0.18 μm CMOS process. The synthesised results show that this design performs an operating frequency of 100 MHz processing rate by consuming only 1.83 mW. Compared with the previous low-complexity designs, this work not only reduces at least 48.2% of gate counts and 96.7% of power consumption but also improves the average CPSNR quality by more than 0.78 dB.
Starting Page	1585
Ending Page	1587
Page Count	3
ISSN	00135194
Volume Number	50
e-ISSN	1350911X
Issue Number	Issue 22, Oct (2014)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/50/22
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2014.1017
Journal	Electronics Letters
Publisher Date	2014-10-14
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Average CPSNR Quality Boundary Detector Boundary Mirror Machine Model CMOS Integrated Circuit CMOS Process Frequency 100 MHz Gate Counts Green Colour Interpolation Model Hardware Cost Reduction Hardware-sharing Technique High-quality Colour Demosaicking Algorithm Identical Direction Technique Image Colour Analysis Image Reconstruction Image Segmentation Integrated Circuit Design Interpolation Interpolation And Function Approximation Layout Low-complexity Colour Demosaicking Algorithm Low-complexity Designs Memory Requirement Modelling And Testing Numerical Analysis Optical, Image And Video Signal Processing Position Information Power Consumption Real-time Video Application Red-blue Colour Interpolation Model Register Bank Design Semiconductor Integrated Circuit Design Size 0.18 Mum Ultra-low-cost Colour Demosaicking VLSI Design Very Large-scale Integration Video Signal Processing VLSI
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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