NDLI: Area-efficient method to approximate two minima for LDPC decoders

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The Journal of Engineering

Area-efficient method to approximate two minima for LDPC decoders

Content Provider	IET Digital Library
Author	Jung, Jaehwan Lee, Youngjoo Park, In Cheol
Abstract	A simple yet effective method is proposed to reduce the hardware complexity of min-sum-based low-density parity-check (LDPC) decoders. The proposed method finds the second minimum from the last four candidates of the first minimum, and can be implemented with only a few hardware components. In the case of 64 inputs, the proposed method reduces the comparators and 2-to-1 multiplexers by 48 and 64% compared to the conventional method that finds two exact minima.
Starting Page	1701
Ending Page	1702
Page Count	2
ISSN	00135194
Volume Number	50
e-ISSN	1350911X
Issue Number	Issue 23, Nov (2014)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/50/23
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2014.1549
Journal	Electronics Letters
Publisher Date	2014-10-28
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Analogue Circuit Approximation Theory Area Efficient Method Code Comparators Comparators (circuits) Digital Circuit Hardware Complexity Hardware Component Interpolation And Function Approximation Min-sum-based LDPC Decoders Multiplexers Multiplexing Equipment Numerical Analysis Parity Check Code Switchgear Two Minima Approximation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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