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Reconfigurable Low-Density Parity-Check (LDPC) Decoder for Multi-Standard 60 GHz Wireless Local Area Networks
| Content Provider | MDPI |
|---|---|
| Author | Lin, Cheng-Hung Su, Hsin-Hao Chen, Tang-Syun Lu, Cheng-Kai |
| Copyright Year | 2022 |
| Description | In this study, a reconfigurable low-density parity-check (LDPC) decoder is designed with good hardware sharing for IEEE 802.15.3c, 802.11ad, and 802.11ay standards. This architecture flexibly supports 12 types of parity-check matrix. The switching network adopts an architecture that can flexibly switch between different inputs and achieves a low hardware complexity. The check node unit adopts a switchable 8/16/32 reconfigurable structure to match different row weights at different code rates and uses the normalised probability min-sum algorithm to simplify the structure of searching for the minimum value. Finally, the chip is implemented using the TSMC 40 nm CMOS process, based on the IEEE 802.11ad standard decoder, extended to support the IEEE 802.15.3c standard, and upwardly compatible with the next-generation advanced standard IEEE 802.11ay. The chip core size was 1.312 mm × 1.312 mm, the operating frequency was 117 MHz when the maximum number of iterations was five with the power consumption of 57.1 mW, and the throughput of 5.24 Gbps and 3.90 Gbsp was in the IEEE 802.11ad and 802.5.3c standards, respectively. |
| Starting Page | 733 |
| e-ISSN | 20799292 |
| DOI | 10.3390/electronics11050733 |
| Journal | Electronics |
| Issue Number | 5 |
| Volume Number | 11 |
| Language | English |
| Publisher | MDPI |
| Publisher Date | 2022-02-26 |
| Access Restriction | Open |
| Subject Keyword | Electronics Error Correction Code Low-density Parity-check Code Min-sum Algorithm Asic Implementation |
| Content Type | Text |
| Resource Type | Article |
