NDLI: Three-dimensional AND flash memory

Content Provider	IET Digital Library
Author	Kim, Y. Park, I. H. Kwon, H. T. Wee, D. Park, B. G.
Abstract	High-density and high-speed charge-trapping AND flash memory array is fabricated for the first time. A reliability of 104 endurance cycles and uniform program/erase characteristics along with a threshold voltage window >3 V is obtained. The AND array has several advantages, such as high read current drivability regardless of the number of word-lines, immunity to back-pattern dependency, and fast bit-sensing speed based on a parallel connected cell array structure, which are highly appropriate for three-dimensional (3D) stacking. Finally, a novel 3D stacked vertical-AND array is proposed to surpass the limitations of the conventional 3D NAND flash memories.
Starting Page	739
Ending Page	741
Page Count	3
ISSN	00135194
Volume Number	53
e-ISSN	1350911X
Issue Number	Issue 11, May (2017)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/53/11
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2017.0465
Journal	Electronics Letters
Publisher Date	2017-05-11
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	3D Stacked Vertical-AND Array Back-pattern Dependency Bit-sensing Speed Endurance Cycle Reliability Flash Memories High-density Charge-trapping AND Flash Memory Array High-speed Charge-trapping AND Flash Memory Array Integrated Circuit Reliability Memory Circuit Parallel Connected Cell Array Structure Parallel Memories Read Current Drivability Reliability Semiconductor Storage Storage Requirements Three-dimensional AND Flash Memory Threshold Voltage Window Uniform Program-erase Characteristic Word-Line
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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