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| Content Provider | IET Digital Library |
|---|---|
| Author | Liu, Dahe Lu, Wengao Yu, Shanzhe Chen, Zhongjian |
| Abstract | A low-power time-to-digital converter (TDC) scheme for column-level single-slope analogue-to-digital converters for infrared imager is presented. This scheme greatly improves the TDC's timing precision with a novel 3-bit fine gray counter, which makes use of multi-phase clocks from a delay-lock-loop. Aimed for 384 × 288 array size uncooled infrared imager with 17 μm pixel pitch, the TDC circuits have been developed and simulated employing 0.18 μm CMOS technology. Compared with conventional two-step TDC methods, this method saves more chip area and reduces the sampling power consumption by >50%, and also eliminates the coarse-fine inconsistency problem with a simulated ±0.1 least-significant-bit differential non-linearity performance. |
| Starting Page | 922 |
| Ending Page | 924 |
| Page Count | 3 |
| ISSN | 00135194 |
| Volume Number | 53 |
| e-ISSN | 1350911X |
| Issue Number | Issue 14, Jul (2017) |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/el/53/14 |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/10.1049/el.2017.0878 |
| Journal | Electronics Letters |
| Publisher Date | 2017-05-31 |
| Access Restriction | Open |
| Rights Holder | © The Institution of Engineering and Technology |
| Subject Keyword | A/D And D/A Convertor Array Size Uncooled Infrared Imager Clocks CMOS Digital Integrated Circuit CMOS Integrated Circuit CMOS Technology Column-level Single-slope Analogue-to-digital Converter Delay Lock Loops Delay-lock-loop DLL-based Grey Counter Image Sonsor Infrared Imaging Low-power Scheme Multiphase Clocks Simulated Least-significant-bit Differential Nonlinearity Performance Size 0.18 Mum Time-digital Conversion Time-to-digital Converter Scheme Timing Precision Two-step TDC Method |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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