NDLI: Deep learning-assisted and combined attack: a novel side-channel attack

Content Provider	IET Digital Library
Author	Yu, W. Chen, J.
Abstract	A deep learning (DL)-assisted and combined side-channel attack (SCA) is exploited to disclose the secret key of an advanced encryption standard (AES) cryptographic circuit with a countermeasure. Different physical leakages of the protected AES cryptographic circuit such as power dissipation and electromagnetic (EM) emission are captured together at first. Then the deep neural networks are utilised to model the relationship between the power noise and the EM noise by analysing the captured power dissipation and EM emission profiles. Ultimately, a special power attack is performed on the protected AES cryptographic circuit to leak the secret key efficiently through using the EM noise to filter the power noise. As demonstrated in the results, for the conventional SCAs, the secret key of the protected AES cryptographic circuit is undisclosed to the adversary even if 1 million plaintexts are enabled. By contrast, only analysing 32,500 number of plaintexts are sufficient to leak the secret key if the DL-assisted and combined SCA is executed.
Starting Page	1114
Ending Page	1116
Page Count	3
ISSN	00135194
Volume Number	54
e-ISSN	1350911X
Issue Number	Issue 19, Sep (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/54/19
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2018.5411
Journal	Electronics Letters
Publisher Date	2018-08-14
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Advanced Encryption Standard Cryptographic Circuit Circuit For Digital Computers Combined Side-channel Attack Cryptography Data Security Deep Learning-assisted Deep Neural Network Electromagnetic Emission EM Emission Profile EM Noise Integrated Circuit Design Knowledge Engineering Technique Learning in AI Neural Computing Technique Neural Nets Physical Leakages Power Aware Computing Power Dissipation Power Electronics Power Noise Power Supply Protected AES Cryptographic Circuit Secret Key Supervisory Circuit
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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