NDLI: Measuring the impact of voltage scaling for soft errors in SRAM-based FPGAs from a designer perspective

Content Provider	IEEE Xplore Digital Library
Author	Tonfat, J. Azambuja, J.R. Nazar, G. Rech, P. Lima Kastensmidt, F. Carro, L. Reis, R. Benfica, J. Vargas, F. Bezerra, E. Frost, C.
Copyright Year	2014
Description	Author affiliation: Centro de Cienc. Computacionais, FURG, Rio Grande, Brazil (Azambuja, J.R.) \|\| Inst. de Inf., UFRGS, Porto Alegre, Brazil (Tonfat, J.; Nazar, G.; Rech, P.; Lima Kastensmidt, F.; Carro, L.; Reis, R.) \|\| Rutherford Appleton Lab., ISIS, Didcot, UK (Frost, C.) \|\| Dept. de Eng. Eletr., PUCRS, Porto Alegre, Brazil (Benfica, J.; Vargas, F.) \|\| Dept. de Eng. Eletr., UFSC, Florianopolis, Brazil (Bezerra, E.)
Abstract	The susceptibility of SRAM-based FPGAs to soft errors increases with each technology node due to the reduction of transistor size, the reduction of voltage supply and the increase of density of devices. This work presents the actual impact of voltage reductions for neutron-induced soft errors in SRAM-based FPGAs. We run neutron radiation experiments with a Spartan-6 (45nm) FPGA at different supply voltages to measure the soft error susceptibility. We measure the variation of the susceptibility of the device (static test) and also of a functional system implemented in it (dynamic test). Experimental results show that 8% reduction in the VDD supply voltage can result in 30% higher device susceptibility. When this is translated to a functional system implemented in the FPGA, the system error rate can have a variation of 55% for a voltage variation of 19%, which has to be taken into account by the designer of the system.
Starting Page	1
Ending Page	6
File Size	489391
Page Count	6
File Format	PDF
ISBN	9781479965403
DOI	10.1109/IMS3TW.2014.6997398
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-17
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Microprocessors neutron radiation FPGA Random access memory voltage scaling Neutrons Routing Table lookup Transistors soft errors Field programmable gate arrays
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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