NDLI: Evaluation of Multi-threaded Processor Designs for Energy Efficient Embedded Systems

Content Provider	IEEE Xplore Digital Library
Author	Ran Zhang Hui Guo
Copyright Year	2013
Description	Author affiliation: Sch. of Comput. Sci. & Eng., Univ. of New South Wales, Sydney, NSW, Australia (Ran Zhang; Hui Guo)
Abstract	Multi-threaded processor designs enable high performance of a single processor core by exploiting both the thread-level and instruction-level parallelism. The performance gain is, however, at the cost of increasing energy consumption, which is not desirable to embedded systems. This paper investigates the energy efficiency of varied multi-threaded processor designs (with the coarse-grained and fine-grained thread switching schemes and different thread numbers). Our experiments, based on a six-stage PISA processor, show that in terms of potential energy saving the coarse-grained design is better than the fine-grained design. Furthermore, for the coarse-grained design, the thread number for the optimal energy efficiency is closely related to the memory access delay. When the memory access latency is small, the low-thread processor appears more energy efficient, When the memory delay increases the high-thread processor becomes superior.
Starting Page	619
Ending Page	626
File Size	329086
Page Count	8
File Format	PDF
ISBN	9780769550961
DOI	10.1109/CSE.2013.97
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-03
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power demand Energy Efficient Embedded Systems Instruction sets Pipelines Switches Hazards Registers Multi-threaded Processor Design Clocks
Content Type	Text
Resource Type	Article

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