NDLI: Low Power Quaternary CMOS Circuit Design

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2008 First International Conference on Emerging Trends in Engineering and Technology

Low Power Quaternary CMOS Circuit Design

Content Provider	IEEE Xplore Digital Library
Author	Madurwar, K.P. Dakhole, P.K.
Copyright Year	2009
Abstract	In this paper voltage mode quaternary circuits are introduced. The quaternary circuits are encoder and decoder circuit, half and full adder circuit. Quaternary operators and elements which are used in the implementation of encoder and decoder circuits, half and full adder are also presented. The set of operators are logical sum, logical product, level up, level down, level conversion operator. Quaternary element is inverter based unit which is also presented. These circuits use two kinds of transistors that is enhancement- mode and depletion-mode transistors.Proposed circuits are static and operate in voltage mode. There no static dissipation. All these circuits are VLSI implementable and do not use clocking. Simulation results of the introduced quaternary voltage-mode circuit, using SPICE level 3, 1.5um technology shows higher speed and better performance than existing one.
Starting Page	168
Ending Page	172
File Size	269355
Page Count	5
File Format	PDF
ISBN	9781424452507
DOI	10.1109/ICETET.2009.140
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-16
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit simulation Voltage Very large scale integration Inverters Circuit synthesis Decoding Adders Logic devices Power engineering and energy Clocks
Content Type	Text
Resource Type	Article

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