NDLI: Design and Analysis of a New Loadless 4T SRAM Cell in Deep Submicron CMOS Technologies

Content Provider	IEEE Xplore Digital Library
Author	Sandeep, R. Deshpande, N.T. Aswatha, A.R.
Copyright Year	2009
Abstract	The goal of this paper is to reduce the power and area of the Static Random Access Memory (SRAM) array while maintaining the competitive performance. Here the various configuration of SRAM array is designed using both the six-transistor (6T) SRAM cell and a new loadless fourtransistor (4T) SRAM cell in deep submicron (130nm, 90nm and 65nm) CMOS technologies. Then it is simulated using HSPICE to check for its functionality, Static Noise Margin (SNM), power dissipation, area occupancy and access time. Except the precharge circuits and the basic storage cells, remaining part of the circuitry is same for both 6T SRAM array and New Loadless 4T SRAM array. Compared to the conventional 6T SRAM array, the new loadless 4T SRAM array consumes less power with less area in deep submicron CMOS technologies. Also the SNM of the new loadless 4T SRAM cell is as good as that of the 6T SRAM cell for higher values of Cell Ratio (CR).
Starting Page	155
Ending Page	161
File Size	387239
Page Count	7
File Format	PDF
ISBN	9781424452507
DOI	10.1109/ICETET.2009.67
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-16
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design engineering SRAM chips Circuit simulation Microprocessors Random access memory CMOS technology Circuit noise Power dissipation MOSFETs Driver circuits
Content Type	Text
Resource Type	Article

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