NDLI: Pruning the Design Space for Just-in-Time Processor Customization

Content Provider	IEEE Xplore Digital Library
Author	Grad, M. Plessl, C.
Copyright Year	2010
Abstract	In this paper we study the feasibility of instruction set specialization for reconfigurable ASIPs at runtime. Applying known instruction set extension algorithms for static ASIPs in this just-in-time CPU specialization context is generally possible. However, the leading state-of-the-art algorithms for this purpose have an exponential algorithmic complexity which is prohibitive when targeting large applications and when the runtime of the customization process is a concern. Hence, we propose effective ways of pruning the design space which can reduce the runtime of instruction set extension algorithms by two orders of magnitude. We evaluate the proposed methods and our tool flow targeting the Wool Cano reconfigurable ASIP architecture with a comprehensive set of applications from the SPEC2006, SciMark2, and MiBench benchmark suites. For some applications we show a 44-fold speedup over a fixed CPU architecture. Finally, we elaborate why linear complexity instruction set extension algorithms are most suitable for just-in-time ASIP specialization.
Starting Page	67
Ending Page	72
File Size	293983
Page Count	6
File Format	PDF
ISBN	9781424495238
DOI	10.1109/ReConFig.2010.19
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-13
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Instruction set extension Software algorithms FPGA Estimation ASIP Complexity theory Just-in-Time Runtime JIT Computer architecture Custom Instructions Hardware ISE
Content Type	Text
Resource Type	Article

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