NDLI: Communication Architectures for Run-Time Reconfigurable Modules in a 2-D Mesh on FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Strunk, J. Hiltscher, J. Rehm, W. Schick, H.
Copyright Year	2010
Abstract	This paper examines the feasibility of utilizing a 2-dimensional (2-D) mesh of run-time reconfigurable modules (RTRMs) on a dynamically and partially reconfigurable (DPR) FPGA for throughput- and real-time-driven tasks. To utilize a 2-D mesh of RTRMs, efficient communication architectures (CA) are required, which will be presented in this work. Such a 2-D mesh of RTRMs on a DPR-capable FPGA can be utilized for throughput-driven tasks to dynamically offload compute functions on a host coupled system, providing multi-user and multi-context execution on behalf of user demands. For embedded systems, it can be utilized as a highly dynamical platform by providing functional enhancement by module replacement during run-time. The exploration also includes a CA for real-time communication between RTRMs in a 2-D mesh. The presented CA design is based on a novel methodology by applying run-time reconfiguration to increase the performance. The design, the implementation, the performance and the resource utilization is shown for throughput- and real-time-driven CAs. As proof of concept, a case study is conducted for the presented CAs on state of the art Virtex-5 FPGAs.
Starting Page	49
Ending Page	54
File Size	251437
Page Count	6
File Format	PDF
ISBN	9781424495238
DOI	10.1109/ReConFig.2010.33
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-13
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Real time systems Embedded systems FPGA run-time reconfiguration 2-D mesh Computer architecture Routing dynamic reconfiguration Resource management communication architecture Field programmable gate arrays Clocks
Content Type	Text
Resource Type	Article

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