NDLI: The State of ZettaRAM

Content Provider	IEEE Xplore Digital Library
Author	Rotenberg, E. Venkatesan, R.V.
Copyright Year	2006
Description	Author affiliation: Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC (Rotenberg, E.)
Abstract	ZettaRAM is a nascent memory technology with roots in molecular electronics. ZettaRAM patents and papers are distilled and consolidated into a unified discussion. Various embodiments and key novel properties are discussed with a bias toward computer architecture and system design implications. Embodiments include transistor-free crossbar arrays and two hybrid molecule/silicon implementations, a flash-like cell and a 1T-1C DRAM cell. Key properties of the core technology include (1) flexibility and precision through molecular engineering, (2) self-assembly, (3) scalability through charge-voltage decoupling, (4) speed/energy tradeoff, (5) multiple discrete states, and (6) mixed molecules. Implications include inexpensive fabrication of high performance memory (by all metrics), practical mixed logic/DRAM, 3D memory, exceeding DRAM power scaling limits, intelligent power management, efficient multi-bit storage, memory hierarchies cohabiting the same space, and multiple virtual products in one physical product. Thus, molecular memory has qualities of a disruptive technology. Computer architects and system designers should play a central role in charting its use
Starting Page	1
Ending Page	5
File Size	6718647
Page Count	5
File Format	PDF
ISBN	1424403901
DOI	10.1109/NANONET.2006.346220
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-09-14
Publisher Place	Switzerland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fabrication Molecular electronics Self-assembly Space technology Scalability Memory management Random access memory Computer architecture Silicon Power engineering and energy
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Tapping ZettaRAM/spl trade/ for low-power memory systems

AMULET3: a high-performance self-timed ARM microprocessor

Scalable Two-Transistor Memory (STTM)

Data replication in banked DRAMs for reducing energy consumption

Modified Hotspot Cache Architecture: A Low Energy Fast Cache for Embedded Processors

ZettaRAM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling

Scheduler-based Multi-Bank Main Memory Configuration for Energy Reduction

1Mb DRAM alternatives

Process technology advanced integration concepts

The State of ZettaRAM

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