NDLI: Modeling and implementation of CPPLL

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Modeling and implementation of CPPLL

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Modeling and implementation of CPPLL

Content Provider	IEEE Xplore Digital Library
Author	Honghui Deng Chao Li Shangming Huang
Copyright Year	2013
Description	Author affiliation: Inst. of VLSI Design, Hefei Univ. of Technol., Hefei, China (Honghui Deng; Chao Li; Shangming Huang)
Abstract	Based on the model of SMIC 0.13 mixed-signal process and its supply voltage is 3.3 V, a Charge Pump Phase-Locked Loop is designed in this paper. The Verilog-A language is applied to build the behavioral modeling for the Charge Pump Phase-Locked Loop, in the bias circuit of Charge Pump a voltage regulation NMOS is added to reduce the charging and discharging current mismatch to less than 0.073%, and the design parameters of the Loop Low-Pass Filter is given in this paper. The Cadence simulation results show that the frequency of the input of the Charge Pump Phase-Locked Loop is 3~160MHz, and the output frequency is 3~400MHz; the maximum division number is 32 and the lock time is less than 22us.
Sponsorship	IEEE Taipei Sect. AP Chapt.
Starting Page	1
Ending Page	5
File Size	258626
Page Count	5
File Format	PDF
ISBN	9781479911110
DOI	10.1109/ICASID.2013.6825303
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-25
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decision support systems Voltage-Controlled Oscillator Verilog-A modeling The Loop Filter CPPLL Hafnium Charge Pump
Content Type	Text
Resource Type	Article

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