NDLI: Soft-error hardened redundant triggered latch

Content Provider	IEEE Xplore Digital Library
Author	Alidash, H.K. Sayedi, S.M. Oklobdzija, V.G.
Copyright Year	2012
Description	Author affiliation: University of Kashan, Iran (Alidash, H.K.) \|\| New Mexico State University, Las Cruces, 88003, USA (Oklobdzija, V.G.) \|\| Isfahan University of Technology, 84156-83111, Iran (Sayedi, S.M.)
Abstract	This paper presents a soft error hardened latch suitable for reliable operation. The proposed circuit is aimed to tackle the particle hit effect on the internal nodes, external logic, as well as the pulse generator circuit. The hardening method is based on redundancy to protect internal nodes and filter out transients resulted from combinational logic. It also uses redundant clocking technique which results in more robustness. The circuit is designed in 90nm CMOS technology and simulated with the HSPICE. Simulation results indicate its lower-power and -delay, and ability to recover from single particle strike on internal and clock nodes, and input transient tolerance up to 120ps.
Starting Page	269
Ending Page	272
File Size	378866
Page Count	4
File Format	PDF
ISBN	9781467326872
e-ISBN	9781467326889
DOI	10.1109/ACQED.2012.6320514
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-07-10
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	SER Latches SEU SET Redundancy Logic gates Robustness Transient analysis Delay Hardened latch Clocks
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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