NDLI: A Proof of concept on defending cold boot attack

Content Provider	IEEE Xplore Digital Library
Author	Joo Guan Ooi Kok Horng Kam
Copyright Year	2009
Description	Author affiliation: Intel Microelectronics Sdn Bhd, Malaysia (Joo Guan Ooi; Kok Horng Kam)
Abstract	DRAM is an essential memory of a modern computer. Microprocessor loads the data which the user requested into DRAM before processing the data. Hence, DRAM contains important information in a computer. Recently, security researchers disclosed that DRAM is vulnerable to attack. Through Cold Boot Attack, DRAM contents can be recovered even after the computer has been powered off for several minutes [1]. The information obtained can be used to circumvent popular disk encryption system such as FileVault and Bit Locker. In this paper, we proposed an enhanced memory architecture which adds a data scrambling / descrambling layer between the microprocessor and DRAM controller to prevent the original data to be stored as cleartext in the DRAM. The original data will be scrambled before writing to DRAM and hence preventing the Cold Boot Attack. This new layer consists of XOR circuit, Galois Field Multiplication of order 128 (GF128) and a Pseudo Random Number Generator (PRNG). The scrambling scheme was selected in this proposal due to its simplicity for proof of concept. Any other cryptography scheme can replace the scrambling / descrambling blocks according to the required level of data protection. The designed blocks were implemented and tested on the Altera DE2 FPGA board using Nios II system. The results confirm that the use of the scrambling / descrambling blocks provides an easy solution with additional level of protection to secure the contents in the DRAM.
Starting Page	330
Ending Page	335
File Size	656317
Page Count	6
File Format	PDF
ISBN	9781424449521
DOI	10.1109/ASQED.2009.5206245
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-07-15
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Microprocessors Data security Memory architecture Circuits Random access memory Information security Writing Cryptography Power system security Protection
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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