NDLI: Low Power Design of a Grating Detection System Chip

Content Provider	IEEE Xplore Digital Library
Author	Li-gang Hou Xiao-hong Peng Wu-chen Wu
Copyright Year	2009
Abstract	This paper forwards a low power design of a grating detection system chip (GDC) on length and angle precision measurement. Traditional grating detection methods are complex, costly, and suffer big power consumption for the complex divide circuit scheme and CPU software compensation. GDC achieves the whole grating detection system function, high speed orthogonal signal handling in a single chip with very low power consumption. It is an application-specific integrated circuit (ASIC), integrated micro controller unit (MCU), power management unit (PMU), two LCD controller, keyboard interface, grating detection unit and other peripherals. Working at 10MHz, GDC can afford 5MHz internal sampling rate and 1.25MHz orthogonal signal from grating sensor. By implementing low power system design, orthogonal signal dividing and Low power divider design, GDC consumes 0.9mw in test mode and 0.2mw in real mode. GDC is tape out in HJTC 180nm process with evaluation kit and demo system developed.
Starting Page	550
Ending Page	554
File Size	1038394
Page Count	5
File Format	PDF
ISBN	9780769535074
DOI	10.1109/CSIE.2009.400
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-03-31
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Application specific integrated circuits Energy consumption Semiconductor device measurement Power measurement Goniometers Length measurement Integrated circuit measurements Gratings Energy management Signal design
Content Type	Text
Resource Type	Article

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