NDLI: VSIB: A Sensor Bus Architecture for Smart-Sensor Network

Content Provider	IEEE Xplore Digital Library
Author	Rahaman, M.S. Chowdhury, M.H. Nasir, I. Lih-Tyng Hwang
Copyright Year	2009
Abstract	There has been a proliferation of real-time sensing application due to the recent technological improvements in small, inexpensive, low-power, and distributed “smart” sensor nodes capable of doing a small amount of data processing and storage. Sensor network coordinates a collection of these sensor nodes to enable a high quality detection and measurement network in great details. Sensors come in great variety with different capabilities from different vendors. Besides, there exists a variety of sensors interfaces i.e. analog (capacitive, inductive, and resistive readout), I2C, SPI, UART, for communicating sensor signals. Therefore, it is difficult to provide the required level of integration and functional flexibility which are of great importance in smart-sensor systems. Due to these various interfaces, the design of the versatile sensor interface bus is of great importance. This paper presents a Versatile Sensor Interface Bus (VSIB) architecture which offers network-independent communication interfaces for connecting sensors to microprocessors, instrumentation systems, and control/field networks. It is shown that it is easier to deploy commonly available sensors with various communication interfaces to a multi-sensor module.
Starting Page	436
Ending Page	439
File Size	400691
Page Count	4
File Format	PDF
ISBN	9780769535074
DOI	10.1109/CSIE.2009.1014
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-03-31
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Coordinate measuring machines Microprocessors Instruments Communication system control Data processing Control systems Capacitive sensors Sensor systems Joining processes Intelligent sensors
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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