NDLI: The Implementation of Low-Power CAM with Fully Adiabatic Driving for Large Node Capacitances

Content Provider	IEEE Xplore Digital Library
Author	Qingbo Xu Lifang Ye Jianping Hu Lijun Huang
Copyright Year	2009
Abstract	An adiabatic 32X32 content-addressable memory (CAM) are designed in this paper, which consists of a CAM storage-cell array, address decoders, bit-lines drivers, and match-line driving circuits. All circuits except for CAM storage cells and driving control circuits for match lines are realized using CPAL (Complementary Pass-Transistor Adiabatic Logic) circuits. The charge of large node capacitances on match lines, bit lines, word lines, and address lines is well recovered in fully adiabatic manner. For comparison, a conventional 32X32 CAM is also implemented using the similar structure. The two CAM cores have been integrated in a test chip with Chartered 0.35um CMOS process. Based on the post-layout simulations, the adiabatic CAM can work very well, and it attains about 86% energy saves compared to the conventional CMOS implementation at 100MHz.
Starting Page	413
Ending Page	417
File Size	656649
Page Count	5
File Format	PDF
ISBN	9780769535074
DOI	10.1109/CSIE.2009.894
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-03-31
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CADCAM Energy consumption Computer aided manufacturing Circuit simulation Adiabatic circuits CMOS process Low power Circuit testing Energy loss CMOS logic circuits Logic circuits Capacitance Content-addressable memories
Content Type	Text
Resource Type	Article

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